Usually, a prescribed voltage (precharge voltage) is applied before write and read on the bit line that transfers the data stored in RAM or another memory cell. The charge that is charged in the capacitive component of the bit line due to application of the precharge voltage is discharged in the process of write operation/read operation, and the fall in voltage of the bit line due to said discharge is used as a write signal or read signal in access to the memory cell.
In recent years, the storage capacity of memories has been on the rise, and loss in electric power due to charging/discharge of the bit line in company with write/read has become a major factor in hampering the efforts in lowering power consumption of large-capacity memories.
In order to suppress such power loss, it is necessary for the vibration amplitude due to charging/discharge of bit line to be as small as possible. A confinement type sense amplifier has been especially developed as a technology for suppressing the discharge current of a bit line in read operation.
FIG. 6 is a schematic block diagram illustrating the constitution of a conventional confinement type sense amplifier.
As shown in FIG. 6, a conventional sense amplifier is composed of p-type MOS transistor Qp3, p-type MOS transistor Qp4, and n-type MOS transistors Qn1-Qn3. An input to this sense amplifier is connected through p-type MOS transistor Qp1 and p-type MOS transistor Qp2 to bit line pair (BL, BLZ).
p-type MOS transistor Qp3 and n-type MOS transistor Qn1 are connected together in series, with node SA at the connection middle point, and their gates are both connected to node SAZ.
p-type MOS transistor Qp4 and n-type MOS transistor Qn2 are connected together in series, with node SAZ at the connection middle point, and their gates are both connected to node SA.
The sources of p-type MOS transistor Qp3 and p-type MOS transistor Qp4 are connected to power source line Vcc. The sources of n-type MOS transistor Qn1 and n-type MOS transistor Qn2 are connected through n-type MOS transistor Qn3 to ground line G.
Node SA is connected through p-type MOS transistor Qp1 to bit line BL. Node SAZ is connected through p-type MOS transistor Qp2 to bit line BLZ.
Sense control signal ENN is input to the gates of p-type MOS transistor Qp1, p-type MOS transistor Qp2, and n-type MOS transistor Qn3.
For the confinement type sense amplifier with the aforementioned constitution, first of all, while a read signal from the memory cell is output to the bit line pair (BL, BLZ), sense control signal ENN is set to a low level. As a result, p-type MOS transistor Qp1 and p-type MOS transistor Qp2 are ON, and n-type MOS transistor Qn3 is OFF. In this case, the read signal from bit line pair (BL, BLZ) is input to node SA and node SAZ. However, since n-type MOS transistor Qn3 is OFF, no discharge current flows from bit line pair (BL, BLZ) to ground line G.
Then, as sense control signal ENN is set to high level from low level, n-type MOS transistor Qn3 is turned from the OFF to the ON state, and power is supplied to the amplifier composed of p-type MOS transistor Qp3, p-type MOS transistor Qp4, n-type MOS transistor Qn1 and n-type MOS transistor Qn2. As a result, the small potential difference between node SA and node SAZ is amplified, one of node SA and node SAZ is pulled up to high level, while the other node is pulled down to low level, and, at the same time, the signal level is maintained. In this case, because p-type MOS transistor Qp1 and p-type MOS transistor Qp2 are turned from the ON to the OFF state at the same time, the discharge current flowing from bit line pair (BL, BLZ) to node SA and node SAZ is suppressed.
However, for the confinement type sense amplifier shown in FIG. 6, because amplification of the read signal is carried out by means of the difference in the minute charge amounts left at node SA and node SAZ after they are cut off from bit line pair (BL, BLZ), detection of the read signal is prone to failure. This is undesired.
FIG. 7 is a diagram illustrating change in the signals at node SA and node SAZ in the sense amplifier shown in FIG. 6.
When word line WL of the memory cell is activated (FIG. 7A), a voltage difference is generated corresponding to the stored data at node SA and node SAZ connected to the bit line pair (BL, BLZ). In the example shown in FIG. 7B, the level of node SA is higher than the level of node SAZ. In this state, when sense control signal ENN becomes high level at time t1 (FIG. 7C), the voltage difference between node SA and node SAZ is amplified, and, in normal operation, as indicated by the solid line in FIG. 7B, node SA becomes high level, and node SAZ becomes low level.
However, when the impedance of p-type MOS transistor Qp1 and p-type MOS transistor Qp2 rises in the period before start of amplification of the voltage difference, node SA and node SAZ enter a floating state. Consequently, as n-type MOS transistor Qn3 is turned ON, said potentials are pulled down to the ground level. In this case, when there is dispersion in the capacitive component, the threshold, and other characteristics of the transistors that form the sense amplifier, the potentials of node SA and node SAZ can be inverted. As a result, an error read signal indicated by the broken line in FIG. 7B is detected. This is undesired.
Although the confinement type sense amplifier can be used as a technology for reducing power consumption, when the power source voltage is lowered, the input voltage of the sense amplifier tends to become smaller. Consequently, the probability of generating said detection error becomes even higher. This is undesired.
The objective of this invention is to solve the aforementioned problems of the prior art by providing a type of sense amplifier that can reduce the detection error of the read signal, as well as a type of bit line circuit and storage device having said sense amplifier.
Another objective of this invention is to provide a method for amplifying a read signal characterized by the fact that it can reduce the detection error of the read signal.